The point A and B at the above diagram represents that Data that need to be sent must be placed at the USIDR ( USI data register ) at least half a clock before USCK clock generation and the commencement of sampling. DI shown above represents the data that comes in the receiver device starting with the MSB. DO shown above represents the data that goes out the sender device starting with MSB. The data register associated with SPI communication is of 8 bit in length. It can be external or internal ( generated by master device ). USCK is the clock cycle that synchronize the communication between devices. The above timing diagram briefs about SPI communication in ATtiny85.
Timing diagram of SPI protocol in ATtiny85: Learn more about SPI communication in detail here.
Additionally Slave Select ( SS ) pin can be configured in the code in case multiple slave devices are involved in the communication. Three mandatory pins of SPI communication in ATtiny85 are DO (PB1), DI (PB0) and USCK (PB2). The master device is responsible for generating the clock pulse to synchronize the communication. In SPI communication the devices take the role of master and slave to establish communication. SPI is a form of serial communication that uses three pins to transfer data. SPI protocol or Three wire Synchronous data transfer mode: This tutorial covers how to operate ATtiny85 in both SPI master and slave mode. This USI module can operate in Two wire Synchronous data transfer ( I2C protocol ) and Three wire Synchronous data transfer ( SPI protocol ) modes. In order to facilitate serial communication in ATtiny85 microcontroller it is equipped with a Universal Serial Interface USI module.
USART, SPI, I2C are some of the popular serial communication protocols in embedded world. Serial communication protocols provides the means to communicate for microcontrollers with external hardware, peripherals or other microcontrollers.
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